Some example embodiments relate to duty cycle correctors, more particularly, to duty cycle correctors using an open-loop mode and configured to modulate a falling edge to correct a duty cycle.
A parallel interface circuit using a double data rate (DDR) mode latches data on a rising edge or a falling edge of a clock. Therefore, when a duty cycle of the clock is 50%, a valid window is large and, as a result, the amount of data error decreases. However, due to design, layout, and various peripheral factors of the interface circuit, the duty cycle of the clock is not always maintained at 50%. A duty cycle corrector is used to correct the duty cycle to 50%.
Generally, the duty cycle corrector uses a closed-loop mode or an open-loop mode. Since the duty cycle corrector using the closed-loop mode uses a feedback signal to correct the duty cycle, there is an advantage that a reliability of the duty cycle correction is improved. However, the closed-loop mode involves a delay to stabilize a feedback circuit, thereby decreasing the speed of duty cycle correction. On the other hand, the duty cycle corrector using the open-loop mode has a higher speed, but is less reliable than the duty cycle corrector using the closed-loop mode.
The duty cycle corrector using the open-loop mode includes a phase interpolator. When the phase interpolator is used, if the clock is out of an interpolating range (that is, the range where a linearity of the interpolating is known), the duty cycle is not corrected because the interpolating is not properly performed. Therefore, when the duty cycle is corrected, it is important to improve both the reliability and the speed of the duty cycle correction.